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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a cmos 220 mhz true-color graphics triple 10-bit video ram-dac adv7150 ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 @ 85 mhz 8-bit pseudo color 15-bit true color applications high resolution, true color graphics professional color prepress imaging general description the adv7150 (adv ? ) is a complete analog output, video ram-dac on a single cmos monolithic chip. the part is spe- cifically designed for use in high performance, color graphics workstations. the adv7150 integrates a number of graphic functions onto one device allowing 24-bit direct true-color op- eration at the maximum screen update rate of 220 mhz. the adv7150 implements 30-bit true color in 24-bit frame buffer designs. the part also supports other modes, including 15-bit true color and 8-bit pseudo or indexed color. either the red, green or blue input pixel ports can be used for pseudo color. (continued on page 12) adv is a registered trademark of analog devices, inc. features 220 mhz, 24-bit (30-bit gamma corrected) true color triple 10-bit gamma correcting d/a converters triple 256 3 10 (256 3 30) color palette ram on-chip clock control circuit palette priority select registers rs-343a/rs-170 compatible analog outputs ttl compatible digital inputs standard mpu l/o interface 10-bit parallel structure 8+2 byte structure programmable pixel port: 24-bit, 15-bit and programmable pixel port: 8-bit (pseudo) pixel data serializer multiplexed pixel input ports; 1:1, 2:1, 4:1 +5 v cmos monolithic construction 160-lead plastic quad flatpack (qfp) thermally enhanced to achieve u jc < 1.0 8 c/w modes of operation 24-bit true color (30-bit gamma corrected) @ 220 mhz @ 170 mhz @ 135 mhz @ 110 mhz functional block diagram 256-color/gamma palette ram 10 10-bit red dac 10-bit blue dac ior 96 c d a b 24 24 24 24 p i x e l p o r t mux 4:1 30 red 256 x 10 mpu port d9 ?d0 10 (8+2) ce r/w c0 c1 loadin clock loadout prgckout sckin sckout clock divide & synchronization circuit ? 32 ? 16, ? 8, ? 4, ? 2 addr (a7?0) revision register command registers (cr1?r3) test registers (mr1) voltage reference circuit ecl to cmos adv7150 v ref r set c omp sync output i pll red (r7?0), green (g7?0), blue (b7?0) color data v aa gnd data to palettes control registers color registers clock control mode register address register green 256 x 10 blue 256 x 10 palette selects (ps0, ps1) id register green register pixel mask register 8 ior iog iog iob iob 10-bit green dac 10 10 blue register red register 8 8 2 8 8 sync blank clock syncout mux 4:1
rev. a C2C adv7150Cspecifications (v aa 1 = +5 v; v ref = +1.235 v; r set = 280 v . ior, iog, iob (r l = 37.5 v , c l = 10 pf); ior , iog , iob = gnd. all specifications t min to t max 2 unless otherwise noted.) parameter all versions unit test conditions/comments static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity 1 lsb max differential nonlinearity 1 lsb max guaranteed monotonic gray scale error 5 % gray scale max coding binary digital inputs (excluding clock, clock ) input high voltage, v inh 2 v min input low voltage, v inl 0.8 v max input current, i in 10 m a max v in = 0.4 v or 2.4 v input capacitance, c in 10 pf max clock inputs (clock, clock ) input high voltage, v inh v aa C 1.0 v min input low voltage, v inl v aa C 1.6 v max input current, i in 10 m a max v in = 0.4 v or 2.4 v input capacitance, c in 10 pf typ digital output output high voltage, v oh 2.4 v min i source = 400 m a output low voltage, v ol 0.4 v max i sink = 3.2 ma floating-state leakage current 20 m a max floating-state output capacitance 20 pf typ analog outputs gray scale current range 15/22 ma min/max output current white level relative to blank 17.69/20.40 ma min/max typically 19.05 ma white level relative to black 16.74/18.50 ma min/max typically 17.62 ma black level relative to blank 0.95/1.90 ma min/max typically 1.44 ma blank level on ior, iob 0/50 m a min/max typically 5 m a blank level on iog 6.29/8.96 ma min/max typically 7.62 ma sync level on iog 0/50 m a min/max typically 5 m a lsb size 17.22 m a typ dac-to-dac matching 3 % max typically 1% output compliance, v oc 0/+1.4 v min/v max output impedance, r out 100 k w typ output capacitance, c out 30 pf max i out = 0 ma voltage reference voltage reference range, v ref 1.14/1.26 v min/v max v ref = 1.235 v for specified perfo rmance input current, i vref +5 m a typ power requirements v aa 5 v nom i aa 3 400 ma max 220 mhz parts i aa 3 370 ma max 170 mhz parts i aa 350 ma max 135 mhz parts i aa 330 ma max 110 mhz parts i aa 315 ma max 85 mhz parts power supply rejection ratio 0.5 %/% max typically 0.12%/%: comp = 0.1 m f dynamic performance clock and data feedthrough 4, 5 C30 db typ glitch impulse 50 pv secs typ dac-to-dac crosstalk 6 C23 db typ notes 1 5% for all versions. 2 temperature range (t min to t max ): 0 c to +70 c; t j (silicon junction temperature) 100 c. 3 pixel port is continuously clocked with data corresponding to a linear ramp. t j = 100 c. 4 clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. glitch impulse includes clock and data feedthrough. 5 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured the 10% and 90% points. timing reference points at 50% for inputs and outputs. 6 dac-to-dac crosstalk is measured by holding one dac high while the other two are making low-to-high and high-to-low transitions. specifications subject to change without notice.
adv7150 C3C rev. a timing characteristics 1 clock control and pixel port 4 220 mhz 170 mhz 135 mhz 110 mhz 85 mhz parameter version version version version version units conditions/comments f clock 220 170 135 110 85 mhz max pixel clock rate t 1 4.55 5.88 7.4 9.1 11.77 ns min pixel clock cycle time t 2 2 2.5 3.2 4 4 ns min pixel clock high time t 3 2 2.5 3 4 4 ns min pixel clock low time t 4 10 10 10 10 10 ns max pixel clock to loadout delay f loadin loadin clocking rate 1:1 multiplexing 110 110 110 110 85 mhz max 2:1 multiplexing 110 85 67.5 55 42.5 mhz max 4:1 multiplexing 55 42.5 33.75 27.5 21.25 mhz max t 5 loadin cycle time 1:1 multiplexing 9.1 9.1 9.1 9.1 9.1 ns min 2:1 multiplexing 9.1 11.76 14.8 18.18 23.53 ns min 4:1 multiplexing 18.18 23.53 29.63 36.36 47.1 ns min t 6 loadin high time 1:1 multiplexing 44444ns min 2:1 multiplexing 45689ns min 4:1 multiplexing 8 9 12 15 18 ns min t 7 loadin low time 1:1 multiplexing 44444ns min 2:1 multiplexing 45689ns min 4:1 multiplexing 8 9 12 15 18 ns min t 8 00000ns min pixel data setup time t 9 55555ns min pixel data hold time t 10 00000ns min loadout to loadin delay t Ct 11 5 t C5 t C5 t C5 t C5 t C5 ns max loadout to loadin delay t pd 6 pipeline delay 1:1 multiplexing 55555 clocks (1 clock = t 1 ) 2:1 multiplexing 66666 clocks 4:1 multiplexing 88888 clocks t 12 10 10 10 10 10 ns max pixel clock to prgckout delay t 13 55555ns max sckin to sckout delay t 14 55555ns min blank to sckin setup time t 15 11111ns min blank to sckin hold time analog outputs 7 220 mhz 170 mhz 135 mhz 110 mhz 85 mhz parameter version version version version version units conditions/comments t 16 15 15 15 15 15 ns typ analog output delay t 17 11111ns typ analog output rise/fall time t 18 15 15 15 15 15 ns typ analog output transition time t sk 22222ns max analog output skew (ior, iog, iob) 00000ns typ mpu ports 8, 9 220 mhz 170 mhz 135 mhz 110 mhz 85 mhz parameter version version version version version units conditions/comments t 19 33333ns minr/ w , c0, c1 to ce setup time t 20 10 10 10 10 10 ns min r/ w , c0, c1 to ce hold time t 21 45 45 45 45 45 ns min ce low time t 22 25 25 25 25 25 ns min ce high time t 23 8 55555ns min ce asserted to databus driven t 24 9 45 45 45 45 45 ns max ce asserted to data valid t 25 9 20 20 20 20 20 ns max ce disabled to databus three-stated 55555ns min t 26 20 20 20 20 20 ns min write data (d0Cd9) setup time t 27 55555ns min write data (d0Cd9) hold time (v aa 2 = +5 v; v ref = +1.235 v; r set = 280 v . ior, iog, iob (r l = 37.5 v , c l = 10 pf); ior , iog , i0b = gnd. all specifications t min to t max 3 unless otherwise noted.)
adv7150 C4C rev. a notes 1 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. ecl inputs (clock, clock ) are v aa C0.8 v to v aa C1.8 v, with input rise/fall times 2 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and out- puts. analog output load 10 pf. databus (d0Cd9) loaded as shown in figure 1. digital output load for loadout, prgckout, sckout, i pll and syncout 30 pf. 2 5% for all versions. 3 temperature range (t min to t max ): 0 c to +70 c; t j (silicon junction temperature) 100 c. 4 pixel port consists of the following inputs: pixel inputs: red [a, b, c, d]; green [a, b, c, d]; blue [a, b, c, d], palette selects: ps0 [a, b, c, d]; ps1 [a, b, c, d]; pixel controls: sync , blank ; clock inputs: clock, clock , loadin, sckin; clock outputs: loadout, prgckout, sckout. 5 t is the loadout cycle time and is a function of the pixel clock rate and the multiplexing mode: 1:1 multiplexing; t = clock = t 1 ns. 2:1 multi- plexing; t = clock 2 = 2 t 1 ns. 4:1 multiplexing; t = clock 4 = 4 t 1 ns. 6 these fixed values for pipeline delay are valid under conditions where t 10 and t -t 11 are met. if either t 10 or t -t 11 are not met, the part will operate but the pipe line de- lay is increased by 2 additional clock cycles for 2:1 mode and is increased by 4 additional clock cycles for 4:1 mode, after calibration is performed. 7 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. output rise/fall time measured between the 10% and 90% points of full-scale transition. transition time measured from the 50% point of full-scale transition to the output remaining within 2% of the final output value (transition time does not include clock and data feedthrough). 8 t 23 and t 24 are measured with the load circuit of figure 1 and defined as the time required for an output to cross 0.4 v or 2.4 v. 9 t 25 is derived from the measured time taken by the data outputs to change by 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapo- lated back to remove the effects of charging the 100 pf capacitor. this means that the time, t 25 , quoted in the timing characteristics is the true value for the device and as such is independent of external databus loading capacitances. specifications subject to change without notice. i sink +2.1v to output pin i source 100pf figure 1. load circuit for databus access and relinquish times t 3 t 2 clock loadout (1:1 multiplexing) loadout (2:1 multiplexing) loadout (4:1 multiplexing) clock t 4 t 1 figure 2. loadout vs. pixel clock input (clock, clock ) pixel input data* loadin t 8 t 9 valid data valid data valid data t 5 t 6 *includes pixel data (r0?7, g0?7, b0?7); palette select inputs (ps0?s1); blank; sync t 7 figure 3. loadin vs. pixel input data
adv7150 C5C rev. a pixel input data* a n+2 b n+2 c n+2 d n+2 clock loadout loadin analog output data t 10 t pd digital input to analog output pipeline a n b n c n d n *includes pixel data (r0?7, g0?7, b0?7); palette select inputs (ps0?s1); blank; sync a n+1 b n+1 c n+1 d n+1 a n b n c n d n a n+1 b n+1 c n+1 d n+1 a n? b n? c n? d n? a n+2 b n+2 c n+2 d n+2 ior, ior iog, iog iob, iob i pll, syncout figure 4. pixel input to analog output pipeline with minimum loadout to loadin delay (4:1 multiplex mode) digital input to analog output pipeline a n+2 b n+2 c n+2 d n+2 clock loadout pixel input data* loadin analog output data a n b n c n d n a n b n c n d n a n+1 b n+1 c n+1 d n+1 a n? b n? c n? d n? a n+2 b n+2 c n+2 d n+2 t pd t t ?t 11 *includes pixel data (r0?7, g0?7, b0?7); palette select inputs (ps0?s1); blank; sync ior, ior iog, iog iob, iob i pll, syncout a n+1 b n+1 c n+1 d n+1 figure 5. pixel input to analog output pipeline with maximum loadout to loadin delay (4:1 multiplex mode)
adv7150 C6C rev. a pixel input data* a n b n t pd a n b n a n-1 b n-1 a n+1 b n+1 a n+2 b n+2 *includes pixel data (r0?7, g0?7, b0?7); palette select inputs (ps0?s1); blank; sync clock loadout loadin analog output data t 10 digital input to analog output pipeline a n+1 b n+1 a n+2 b n+2 ior, ior iog, iog iob, iob i pll, syncout figure 6. pixel input to analog output pipeline with minimum loadout to loadin delay (2:1 multiplex mode) clock loadout pixel input data* loadin analog output data t pd digital input to analog output pipeline a n b n a n+1 b n+1 a n b n a n-1 b n-1 a n+1 b n+1 a n+2 b n+2 *includes pixel data (r0?7, g0?7, b0?7); palette select inputs (ps0?s1); blank; sync t t ?t 11 a n+2 b n+2 ior, ior iog, iog iob, iob i pll, syncout figure 7. pixel input to analog output pipeline with maximum loadout to loadin delay (2:1 multiplex mode)
adv7150 C7C rev. a t 12 clock prgckout (clock/4) prgckout (clock/8) prgckout (clock/16) prgckout (clock/32) figure 8. pixel clock input vs. programmable clock output (prgckout) sckin end of scan line (n) t 13 sckout start of scan line (n+1) blanking period t 15 t 14 blank figure 9. video data shift clock input (sckin) & blank vs. video data shift clock output (sckout) clock t 16 analog outputs t 17 t 18 10 % 50 % 90 % full-scale transition white level black level ior, ior iog, iog iob, iob i pll, syncout note: this diagram is not to scale. for the purposes of clarity, the analog output waveform is magnified in time and amplitude w.r.t the clock waveform. i pll and syncout are digital video output signals. t 16 is the only relevent output timing specification for i pll and syncout. figure 10. analog output response vs. clock
adv7150 C8C rev. a recommended operating condition parameter symbol min typ max units power supply v aa 4.75 5.00 5.25 volts ambient operating temperature t a 0 +70 c reference voltage v ref 1.14 1.235 1.26 volts output load r l 37.5 w warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv7150 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v voltage on any digital pin . . . . gnd C 0.5 v to v aa + 0.5 v ambient operating temperature (t a ) . . . . . C55 c to +125 c storage temperature (t s ) . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . +260 c vapor phase soldering (1 minute) . . . . . . . . . . . . . . . +220 c analog outputs to gnd 2 . . . . . . . . . . . . . gnd C 0.5 to v aa notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. ordering guide 1, 2, 3 speed 220 mhz adv7150ls220 110 mhz adv7150ls110 170 mhz ADV7150LS170 85 mhz adv7150ls85 135 mhz adv7150ls135 notes 1 adv7150 is packaged in a 160-pin plastic quad flatpack, qfp. 2 all devices are specified for 0 c to +70 c operation. 3 contact sales office for latest information on package design. 16-lead qfp configuration row d pin no. 1 identifier row a row c adv7150 qfp top view (not to scale) row b 160 121 41 80 1 40 120 81 t 19 t 20 valid control data t 21 t 22 t 23 t 26 t 25 t 27 d0?9 (read mode) d0?9 (write mode) ce r/w, c0, c1 r/w = 1 r/w = 0 t 24 figure 11. microprocessor port (mpu) interface timing
adv7150 C9C rev. a adv7150 pin assignments pin pin pin pin number mnemonic number mnemonic number mnemonic number mnemonic 1g3 a 41 ps1 d 81 nc 121 r1 a 2g3 b 42 b0 a 82 d2 122 r1 b 3g3 c 43 b0 b 83 nc 123 r1 c 4g3 d 44 b0 c 84 gnd 124 r1 d 5g4 a 45 b0 d 85 gnd 125 r2 a 6g4 b 46 b1 a 86 gnd 126 r2 b 7g4 c 47 b1 b 87 d3 127 r2 c 8g4 d 48 b1 c 88 d4 128 r2 d 9g5 a 49 b1 d 89 d5 129 r3 a 10 g5 b 50 b2 a 90 v aa 130 r3 b 11 g5 c 5 1 b2 b 91 d6 131 r3 c 12 g5 d 52 b2 c 92 d7 132 r3 d 13 clock 53 b2 d 93 d8 133 r4 a 14 clock 54 b3 a 94 d9 134 r4 b 15 loadin 55 b3 b 95 gnd 135 r4 c 16 loadout 56 b3 c 96 gnd 136 r4 d 17 v aa 57 b3 d 97 gnd 137 r5 a 18 v aa 58 b4 a 98 iob 138 r5 b 19 prgckout 59 b4 b 99 ior 139 r5 c 20 sckin 60 b4 c 100 iog 140 r5 d 21 sckout 61 b4 d 101 iob 141 r6 a 22 syncout 62 b5 a 102 iog 142 r6 b 23 gnd 63 b5 b 103 v aa 143 r6 c 24 gnd 64 b5 c 104 v aa 144 r6 d 25 gnd 65 b5 d 105 v aa 145 r7 a 26 g6 a 66 b6 a 106 ior 146 r7 b 27 g6 b 67 b6 b 107 comp 147 r7 c 28 g6 c 68 b6 c 108 v ref 148 r7 d 29 g6 d 69 b6 d 109 r set 149 g0 a 30 g7 a 70 b7 a 110 i pll 150 g0 b 31 g7 b 71 b7 b 111 gnd 151 g0 c 32 g7 c 72 b7 c 112 v aa 152 g0 d 33 g7 d 73 b7 d 113 v aa 153 g1 a 34 ps0 a 74 ce 114 v aa 154 g1 b 35 ps0 b 75 r/ w 115 sync 155 g1 c 36 ps0 c 76 c0 116 blank 1 56 g1 d 37 ps0 d 77 c1 117 r0 a 157 g2 a 38 ps1 a 78 d0 118 r0 b 158 g2 b 39 ps1 b 79 d1 119 r0 c 159 g2 c 40 ps1 c 80 gnd 120 r0 d 160 g2 d nc = no connect.
adv7150 C10C rev. a pin function description mnemonic function red (r0 a . . . r0 d Cr7 a . . . r7 d ), pixel port (ttl compatible inputs): 96 pixel select inputs, with 8 bits each for red, 8 green (g0 a . . . g0 d Cg7 a . . . g7 d ), bits for green and 8 bits for blue. each bit is multiplexed [a-d] 4:1, 2:1 or 1:1. it can blue (b0 a . . . b0 d Cb7 a . . . b7 d ) be configured for 24-bit true-color data, 8-bit pseudo-color data and 15-bit true-color data formats. pixel data is latched into the device on the rising edge of loadin. ps0 a . . . ps0 d , ps1 a . . . ps1 d palette priority selects (ttl compatible inputs): these pixel port select inputs deter- mine whether or not the devices pixel data port is selected on a pixel by pixel basis. the palette selects allow switching between multiple palette devices. the device can be preprogrammed to completely shut off the dac analog outputs. if the values of ps0 and ps1 match the values programmed into bits mr16 and mr17 of the mode regis- ter, then the device is selected. each bit is multiplexed [a-d] 4:1, 2:1 or 1:1. ps0 and ps1 are latched into the device on the rising edge of loadin. loadin pixel data load input (ttl compatible input). this input latches the multiplexed pixel data, including ps0Cps1, blank and sync into the device. loadout pixel data load output (ttl compatible output). this output control signal runs at a divided down frequency of the pixel clock input. its frequency is a function of the multiplex rate. it can be used to directly or indirectly drive loadin f loadout = f clock /m where m = 1 for 1:1 multiplex mode where m = 2 for 2:1 multiplex mode where m = 4 for 4:1 multiplex mode. prgckout programmable clock output (ttl compatible output). this output control signal runs at a divided down frequency of the pixel clock input. its frequency is user programmable and is determined by bits cr30 and cr31 of command register 3 f prgckout = f clock /n where n = 4, 8, 16 and 32. sckin video shift clock input (ttl compatible input). the signal on this input is internally gated synchronously with the blank signal. the resultant output, sckout, is a video clocking signal that is stopped during video blanking periods. sckout video shift clock output (ttl compatible output). this output is a synchronously gated version of sckin and blank . sckout, is a video clocking signal that is stopped during video blanking periods. clock, clock clock inputs (ecl compatible inputs). these differential clock inputs are designed to be driven by ecl logic levels configured for single supply (+5 v) operation. the clock rate is normally the pixel clock rate of the system. blank composite blank (ttl compatible input). this video control signal drives the analog outputs to the blanking level. sync composite-sync input (ttl compatible input). this video control signal drives the iog analog output to the sync level. it is only asserted during the blanking period. cr22 in command re gister 2 must be set if sync is to be decoded onto the analog output, otherwise the sync input is ignored. syncout composite-sync output (ttl compatible output). this video output is a delayed version of sync . the delay corresponds to the number of pipeline stages of the device. d0Cd9 databus (ttl compatible input/output bus). data, including color palette values and device control information is written to and read from the device over this 10-bit, bidi- rectional databus. 10-bit data or 8-bit data can be used. the databus can be configured for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. any un- used bits of the databus should be terminated through a resistor to either the digital power plane (v cc ) or gnd. ce chip enable (ttl compatible input). this input must be at logic 0, when writing to or reading from the device over the databus (d0Cd9). internally, data is latched on the rising edge of ce .
adv7150 C11C rev. a mnemonic function r/ w read/write control (ttl compatible input). this input determines whether data is written to or read from the devices registers and color palette ram. r/ w and ce must be at logic 0 to write data to the part. r/ w must be at logic 1 and ce at logic 0 to read from the device. c0, c1 command controls (ttl compatible inputs). these inputs determine the type of read or write operation being performed on the device over the databus (see interface truth table). data on these inputs is latched on the falling edge of ce . ior; ior , iog; iog , iob; red, green and blue current outputs (high impedance current sources). these rgb iob video outputs are specified to directly drive rs-343a and rs-170 video levels into dou- bly terminated 75 w loads. ior , iog and iob are the complementary outputs of ior, iog and iob. these out- puts can be tied to gnd if it is not required to use differential outputs. v ref voltage reference input (analog input). an external 1.235 v voltage reference is re- quired to drive this input. an ad589 (2-terminal voltage reference) or equivalent is rec- ommended. (note: it is not recommended to use a resistor network to generate the voltage reference.) r set output full-scale adjust control (analog input). a resistor connected between this pin and analog ground controls the absolute amplitude of the output video signal. the value of r set is derived from the full-scale output current on iog according to the following equations: r set ( w ) = c1 v ref /iog (ma); sync on green r set ( w ) = c2 v ref /iog (ma); no sync on green. full-scale output currents on ior and iob for a particular value of r set are given by: ior ( ma )= c 2 v ref (v)/r set ( w ) and iob ( ma ) = c 2 v ref (v)/r set ( w ) where c 1 = 6,050; pedestal = 7.5 ire where c1 = 5,723; pedestal = 0 ire and where c 2 = 4,323; pedestal = 7.5 ire where c1 = 3,996; pedestal = 0 ire. comp compensation pin. a 0.1 m f capacitor should be connected between this pin and v aa . i pll phase lock loop output current (high impedance current source). this output is used to enable multiple adv7150s along with adv7151s to be synchronized together with pixel resolution when using an external pll. this output is triggered either from the falling edge of sync or blank as determined by bit cr21 of command register 2. when activated, it supplies a current corresponding to: i pll ( ma ) = 1,728 v ref ( v )/ r set ( w ) when not using the i pll function, this output pin should be tied to gnd. v aa power supply (+5 v 5%). the part contains multiple power supply pins, all should be connected together to one common +5 v filtered analog power supply. gnd analog ground. the part contains multiple ground pins, all should be connected together to the systems ground plane.
adv7150 C12C rev. a circuit details and operation overview digital video or pixel data is latched into the adv7150 over the devices pixel port. this data acts as a pointer to the onboard color palette ram. the data at the ram address pointed to is latched into the digital-to-analog converters (dacs) and output as an rgb analog video signal. for the purposes of clarity of description, the adv7150 is bro- ken down into three separate functional blocks. these are: 1. pixel port and clock control circuit 2. mpu port, registers and color palette 3. digital-to-analog converters and video outputs table i shows the architectural and packaging differences be- tween other devices in the adv715x series of workstation parts. (for more details consult the relevant data sheets.) table i. architectural and packaging differences of the adv715x series description adv7150 adv7152* adv7151* 24-bit gamma true color ? ? 24-bit standard true color ? ? 8-bit gamma pseudo color ? ? ? 8-bit standard pseudo color ? ? ? 15-bit true color ? ? 220 mhz C true color ? ? 220 mhz C pseudo color ? ? ? triple 10-bit dacs ? ? ? 4:1 multiplexing ? ? 2:1 multiplexing ? ? ? 1:1 multiplexing ? ? ? 160-lead qfp ? 100-lead qfp ? ? *see adv7151 and adv7150 data sheets for more information on these parts. (continued from page 1) the device consists of three, high speed, 10-bit, video d/a con- verters (rgb), three 256 10 (one 256 30) color look-up tables, palette priority selects, a pixel input data multiplexer/ serializer and a clock generator/divider circuit. the adv7150 is capable of 1:1, 2:1 and 4:1 multiplexing. the onboard palette priority select inputs enable multiple palette devices to be con- nected together for use in multipalette and window applications. the part is controlled and programmed through the micropro- cessor (mpu) port. the part also contains a number of onboard test registers, associated with self diagnostic testing of the de- vice. the individual red, green and blue pixel input ports al- low true-color, image rendition. true-color image rendition, at speeds of up to 220 mhz, is achieved through the use of the onboard data multiplexer/serializer. the pixel input ports flex- ibility allows for direct interface to most standard frame buffer memory configurations. the 30 bits of resolution, associated with the color look-up table and triple 10-bit dac, realizes 24-bit true-color resolution, while also allowing for the onboard implementation of lineariza- tion algorithms, such as gamma-correction. this allows effec- tive 30-bit true-color operation. the on-chip video clock controller circuit generates all the inter- nal clocking and some additional external clocking signals. an external ecl oscillator source with differential outputs is all that is required to drive the clock and clock inputs of the adv7150. the part can also be driven by an external clock gen- erator chip circuit, such as the ad730. the adv7150 is capable of generating rgb video output sig- nals which are compatible with rs-343a and rs-170 video standards, without requiring external buffering. test diagnostic circuitry has been included to complement the users system level debugging. the adv7150 is fabricated in a +5 v cmos process. its monolithic cmos construction ensures greater functionality with low power dissipation. the adv7150 is packaged in a plastic 160-pin power quad flat- pack (qfp). superior thermal dissipation is achieved by inclu- sion of a copper heatslug, within the standard package outline to which the die is attached. pixel port and clock control circuit the pixel port of the adv7150 is directly interfaced to the video/graphics pipeline of a computer graphics subsystem. it is connected directly or through a gate array to the video ram of the systems frame-buffer (video memory). the pixel port on the device consists of: color data red, green, blue pixel controls sync , blank palette selects ps0Cps1 the associated clocking signals for the pixel port include: clock inputs clock, clock , loadin, sckin clock outputs loadout, prgckout, sckout these onboard clock control signals are included to simplify in- terfacing between the part and the frame buffer. only two con- trol input signals are necessary to get the part operational, clock and clock (ecl levels). no additional signals or external glue logic are required to get the pixel port & clock control circuit of the part operational . pixel port (color data) the adv7150 has 96 color data inputs. the part has four (for 4:1 multiplexing) 24-bit wide direct color data inputs. these are user programmed to support a number of color data formats in- cluding 24-bit true color, 15-bit true color and 8-bit pseudo color (see color data formats section) in 4:1, 2:1 and 1:1 multiplex modes. a b c d multiplexer 24 24 24 24 24 red green blue 8 8 8 figure 12. multiplexed color inputs for the adv7150
adv7150 C13C rev. a multiplexing the onboard multiplexers of the adv7150 eliminate the need for external data serializer circuits. multiple video memory devices can be connected, in parallel, directly to the device. vram (bank a) vram (bank b) vram (bank c) vram (bank d) multiplexer 24 24 24 24 24 33mhz 33mhz 33mhz 33mhz adv7150 video memory/ frame buffer 132 mhz (4 x 33 mhz) figure 13. direct interfacing of video memory to adv7150 figure 13 shows four memory banks of 33 mhz memory con- nected to the adv7150, running in 4:1 multiplex mode, giving a resultant pixel or dot clock rate of 132 mhz. as mentioned in the previous section, the adv7150 supports a number of color data formats in 4:1, 2:1 and 1:1 multiplex modes. in 1:1 multiplex mode, the adv7150 is clocked using the loadin signal. this means that there is no requirement for dif- ferential ecl inputs on clock and clock . the pixel clock is connected directly to loadin. (note: the ecl c lock can still be used to generate loadout prgckout, etc.) clock control circuit the adv7150 has an integrated clock control circuit (figure 14). this circuit is capable of both generating the adv7150s internal clocking signals as well as external graphics subsystem clocking signals. total system synchronization can be attained by using the parts output clocking signals to drive the control- ling graphics processors master clock as well as the video frame buffers shift clock signals. clock adv7150 clock divide by n ( ? n) loadout divide by m ( ? m) prgckout loadin sckout sckin blank latch enable sync to color data multiplexer ecl to ttl m is a function of multiplex rate m = 4 in 4:1 multiplex mode m = 2 in 2:1 multiplex mode m = 1 in 1:1 multiplex mode n is independently programmable n= (4, 8, 16, 32) figure 14. clock control circuit of the adv7150 color data is latched into the parts pixel port on every rising edge of loadin (see timing waveform, figure 3). the required frequency of loadin is determined by the multiplex rate, where: f loadin = f clock /4 4:1 multiplex mode f loadin = f clock /2 2:1 multiplex mode f loadin = f clock 1:1 multiplex mode other pixel data signals latched into the device by loadin include sync , blank and ps0Cps1. internally, data is pipelined through the part by the differential pixel clock inputs, clock and clock . the loadin con- trol signal needs only have a frequency synchronous relationship to the pixel clock (see pipeline delay & onboard calibra- tion section). a completely phase independent loadin signal can be used with the adv7150, allowing the clock to occur anywhere during the loadin cycle. alternatively, the loadout signal of the adv7150 can be used. loadout can be connected either directly or indirectly to loadin. its frequency is automatically set to the correct loadin requirement. sync , blank the blank and sync video control signals drive the analog outputs to the blanking and sync levels respectively. these signals are latched into the part on the rising edge of loadin. the sync information is encoded onto the iog analog signal when bit cr22 of command register 2 is set to a logic 1. the sync input is ignored if cr22 is set to 0. syncout in some applications where it is not permissible to encode sync on green (iog), syncout can be used as a separate ttl digital sync output. this has the advantage over an inde- pendent (of the adv7150) sync in that it does not necessitate knowing the absolute pipeline delay of the part. this allows complete independence between loadin/pixel data and clock. the sync input is connected to the device as normal with bit cr22 of command register 2 set to 0 thereby pre- venting sync from being encoded onto iog. bit cr12 of command register 1 is set to 1, enabling syncout . the output signal generates a ttl syncout with correct pipeline delay that is capable of directly driving the composite sync signal of a computer monitor. ps0Cps1 (palette priority select inputs) these pixel port select inputs determine whether or not the de- vice is selected. these controls effectively determine whether the devices rgb analog outputs are turned-on or shut down. when the analog outputs are shut down, ior, iog and iob are forced to 0 ma regardless of the state of the pixel and control data inputs. this state is determined on a pixel by pixel basis as the ps0Cps1 inputs are multiplexed in exactly the same format as the pixel port color data. these controls allow for switching between multiple palette devices (see appendix 4). if the values of ps0 and ps1 match the values programmed into bits mr16 and mr17 of the mode register, then the device is selected, if there is no match the device is effectively shut down.
adv7150 C14C rev. a clock, clock inputs the clock control circuit is driven by the pixel clock inputs, clock and clock . these inputs can be driven by a differ- ential ecl oscillator running from a +5 v supply. alternatively, the adv7150 clock inputs can be driven by a programmable clock generator (figure 15), such as the ics1562. the ics1562 is a monolithic, phase-locked-loop, clock generator chip. it is capable of synthesizing differential ecl output frequencies in a range up to 220 mhz from a single low frequency reference crystal. v cc gnd 220 w 330 w gnd +5v clock clock clock generator +5v gnd v aa v clock adv7150 gnd d0-d3 cs r/w ecl out+ v ref out v ref v aa 0.1 m f low frequency oscillator v cc gnd 220 w 330 w ecl out figure 15. pll generator driving clock, clock of the adv7150 clock control signals loadout the adv7150 generates a loadout control signal which runs at a divided down frequency of the pixel clock. the frequency is automatically set to the programmed multiplex rate, controlled by cr37 and cr36 of command register 3. f loadout = f clock /4 4:1 multiplex mode f loadout = f clock /2 2:1 multiplex mode f loadout = f clock 1:1 multiplex mode the loadout signal is used to directly drive the loadin pixel latch signal of the adv7150. this is most simply achieved by tying the loadout and loadin pins together. alterna- tively, the loadout signal can be used to drive the frame buffers shift clock signals, returning to the loadin input de- layed with respect to loadout. if it is not necessary to have a known fixed number of pipeline delays, then there is no limitation on the delay between load- out and loadin (loadout(1) and loadout(2)). loadin and pixel data must conform to the setup and hold times (t 8 and t 9 ). if, however, it is required that the adv7150 has a fixed number of pipeline delays (t pd ), loadout and loadin must con- form to timing specifications t 10 and t -t 11 as illustrated in fig- ures 4 to 7. loadout loadin adv7150 video frame buffer loadout loadin adv7150 video frame buffer loadout(1) loadout(2) pixel data pixel data loadin loadout loadout(1) loadout(2) delay figure 16. l oadout vs. pixel clock input (clock, clock ) prgckout the prgckout control signal outputs a user programmable clock frequency. it is a divided down frequency of the pixel clock (see figure 8). the rising edge of prgckout is synchronous to the rising edge of loadout f prgckout = f clock /n where n = 4, 8, 16 or 32. one application of the prgckout is to use it as the master clock frequency of the graphics subsystems processor or controller. sckin, sckout these video memory signals are used to minimize external sup- port chips. figure 17 illustrates the function that is provided. an input signal applied to sckin is synchronously and-ed with the video blanking signal ( blank ). the resulting signal is output on sckout. figure 9 of the timing waveform section shows the relationship between sckout, sckin and blank . sckout sckin blank latch enable sync figure 17. sckout generation circuit the sckout signal is essentially the video memory shift con- trol signal. it is stopped during the screen retrace. figure 18 shows a suggested frame buffer to adv7150 interface. this is a minimum chip solution and allows the adv7150 control the overall graphics system clocking and synchronization. loadout sckout adv7150 video frame buffer pixel data loadin sckin blank figure 18. adv7150 interface using sckin and sckout
adv7150 C15C rev. a pipeline delay and onboard calibration the adv7150 has a fixed number of pipeline delays (t pd ), so long as timings t 10 and t -t 11 are met. however, if a fixed pipeline delay is not a requirement, timings t 10 and t -t 11 can be ignored, a calibration cycle must be run and there is no restriction on loadin to loadout timing. if timings t 10 and t -t 11 are not met, the part will function correctly though with an increased number of pipeline delays, t pd + n clocks (for 4:1 mode n = 4, for 2:1 mode n = 2, for 1:1 mode n = 0). the adv7150 has onboard calibration circuitry which synchronizes pixel data and loadin with the internal adv7150 clocking signals. calibra- tion can be performed in two ways: during the devices initializa- tion sequence by toggling two bits of the mode register, mr10 followed by mr15, or by writing a 1 to bit cr10 of co mmand register 1 which executes a calibration on every vertical sync. color video modes the adv7150 supports a number of color video modes all at the maximum video rate. command bits cr24Ccr27 of command register 2 along with bit mr11 of mode register 1 determine the color mode. 24-bit gamma true color (cr25, cr26, cr27 = 1, 1, 1 and mr11 = 1) the part is set to 24-bit/30-bit true-color operation. the pixel port accepts 24 bits of color data which is directly mapped to the look-up table ram. the look-up table is configured as a 256 location by 30 bits deep ram (10 bits each for red, green and blue). the output of the ram drives the dacs with 30-bit data (10 bits each for red, green and blue). the ram is preloaded with a user determined, nonlinear function, such as a gamma correction curve. 10 10-bit red dac 10-bit blue dac red 256 x 10 green 256 x 10 blue 256 x 10 8 10-bit green dac 10 10 8 8 24-bit color data 24-bit to 30-bit look-up table 30-bit color data analog video outputs red out green out blue out figure 19. 24-bit to 30-bit true-color configuration this mode allows for the display of full 24-bit, gamma- corrected true-color images. 24-bit standard true color (cr25, cr26, cr27 = 1, 1, 1 and mr11 = 0) this mode sets the part into direct 24-bit true-color operation. the pixel port accepts 24 bits of color data which is directly mapped to look-up table ram. the look-up table is con- figured as a 256 location by 24 bits deep ram (8 bits each for red, green and blue) and essentially acts as a bypass ram. the output of the ram drives the dacs with 24-bit data (8 bits each for red, green and blue). the ram is preloaded with a linear function. this mode allows for the display of full 24-bit true-color images. 8 8-bit red dac 8-bit blue dac red 256 x 8 green 256 x 8 blue 256 x 8 8 8-bit green dac 8 8 8 8 red out green out blue out 24-bit color data 24-bit to 24-bit look-up table 24-bit color data analog video outputs figure 20. 24-bit to 24-bit direct true-color configuration 8-bit gamma pseudo color (cr25, cr26, cr27 = x, 0, 0 or x, 1, 0 or x, 0, 1 and mr11 = 1) this mode sets the part into 8-bit pseudo-color operation. the pixel port accepts 8 bits of pixel data which indexes a 30-bit word in the look-up table ram. the look-up table is con- figured as a 256 location by 30 bits deep ram (10 bits each for red, green and blue). the output of the ram drives the dacs with 30-bit data (10 bits each for red, green and blue). 10 10-bit red dac 10-bit blue dac red 256 x 10 green 256 x 10 blue 256 x 10 10-bit green dac 10 10 8 red out green out blue out 8-bit pixel data 8-bit to 30-bit look-up table 30-bit color data analog video outputs figure 21. 8-bit to 30-bit pseudo-color configuration this mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors. 8-bit standard pseudo color (cr25, cr26, cr27 = x, 0, 0 or x, 1, 0 or x, 0, 1 and mr11 = 0) this mode sets the part into 8-bit pseudo-color operation. the pixel port accepts 8 bits of pixel data which indexes a 24-bit word in the look-up table ram. the look-up table is con- figured as a 256 location by 24 bits deep ram (10 bits each for red, green and blue). the output of the ram drives the dacs with 24-bit data (8 bits each for red, green and blue). 8 8-bit red dac 8-bit blue dac red 256 x 8 green 256 x 8 blue 256 x 8 8-bit green dac 8 8 8 red out green out blue out 8-bit pixel data 8-bit to 24-bit look-up table 24-bit color data analog video outputs figure 22. 8-bit to 24-bit pseudo-color configuration this mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors.
adv7150 C16C rev. a 15-bit gamma true color (cr24, cr25, cr26, cr27 = 0, 0, 1, 1 or 1, 0, 1, 1 and mr11 = 1) the part is set to 15-bit true-color operation. the pixel port accepts 15-bits of color data which is mapped to the 5 lsbs of each of the red, green and blue palettes of the look-up table ram. the look-up table is configured as a 32 location by 30 bits deep ram (10 bits each for red, green and blue). the output of the ram drives the dacs with 30-bit data (10 bits each for red, green and blue). 10 10-bit red dac 10-bit blue dac red 32 x 10 green 32 x 10 blue 32 x 10 5 10-bit green dac 10 10 5 5 red out green out blue out 15-bit color data 15-bit to 30-bit look-up table 30-bit color data analog video outputs figure 23. 15-bit to 30-bit true-color configuration this mode allows for the display of 15-bit, gamma-corrected true-color images. 15-bit standard true color (cr24, cr25, cr26, cr27 = 0, 0, 1, 1 or 1, 0, 1, 1 and mr11 = 0) the part is set to 15-bit true-color operation. the pixel port accepts 15 bits of color data which is mapped to the 5 lsbs of each of the red, green and blue palettes of the look-up table ram. the look-up table is configured as a 32 location by 24 bits deep ram (8 bits each for red, green and blue). the output of the ram drives the dacs with 24-bit data (8 bits each for red, green and blue). 8 8-bit red dac 8-bit blue dac red 32 x 8 green 32 x 8 blue 32 x 8 5 8-bit green dac 8 8 5 5 red out green out blue out 15-bit color data 15-bit to 24-bit look-up table 24-bit color data analog video outputs figure 24. 15-bit to 24-bit true-color configuration r4 r3 r2 r1 r0 x x x g1 g0 g4 x g3 g2 x x x x x b4 b3 b2 b1 b0 pixel input data location "0" location "31" 256 x 10 ram (red lut) 10 to red dac 0 0 0 r4 r3 r2 r1 r0 location "0" location "31" 256 x 10 ram (green lut) 10 to green dac 0 0 0 g4 g3 g2 g1 g0 location "0" location "31" 256 x 10 ram (blue lut) 10 to blue dac 0 0 0 b4 b3 b2 b1 b0 5 5 5 pin assign- ments data latched to pixel port data latches first 32 locations of ram data internally shifted to 5 lsbs b5 b4 b3 b2 b1 b0 x x x x x x x x b6 b7 g6 g5 g4 g3 g2 g1 g0 r6 r5 r4 r3 r2 r1 r0 r4 r3 r2 r1 r0 g4 g3 g2 x g1 g0 b4 b3 b2 b1 b0 g7 r7 figure 25. 15-bit true-color mapping using r3Cr7, g3Cg7 and b3Cb7 this mode allows for the display of 15-bit true-color images. pixel port mapping the pixel data to the adv7150 is automatically mapped in the parts pixel port as determined by the pixel data mode pro- grammed (bits cr24Ccr27 of command register 2). pixel data in the 24-bit true-color modes is directly mapped to the 24 color inputs r0Cr7, g0Cg7 and b0Cb7. there are three modes of operation for 8-bit pseudo color. each mode maps the input pixel data differently. data can be input one of the three color channels, r0Cr7 or g0Cg7 or b0Cb7.
adv7150 C17C rev. a r4 r3 r2 r1 r0 g4 g2 g3 x g1 g0 g4 b4 b3 b2 b1 x x x x x x x x pixel input data location "0" location "31" 256 x 10 ram (red lut) 10 to red dac 0 0 0 r4 r3 r2 r1 r0 location "0" location "31" 256 x 10 ram (green lut) 10 to green dac 0 0 0 g4 g3 g2 g1 g0 location "0" location "31" 256 x 10 ram (blue lut) 10 to blue dac 0 0 0 b4 b3 b2 b1 b0 5 5 5 pin assign- ments data latched to pixel port data latches first 32 locations of ram data internally shifted to 5 lsbs b5 b4 b3 b2 b1 b0 x x x x x x x x b6 b7 g6 g5 g4 g3 g2 g1 g0 r6 r5 r4 r3 r2 r1 r0 r4 r3 r2 r1 r0 g4 g3 g2 x g1 g0 b4 b3 b2 b1 b0 g7 r7 figure 26. 15-bit true-color mapping using r0Cr7 and g0Cg6 the part has two modes of operation for 15-bit true color. in the first mode, data is input to the device over the red, green and blue channel (r3Cr7, g3Cg7 and b3Cb7) and is internally mapped to locations 0 to 31 of the look-up table (lut) ac- cording to figure 25. in the second mode, data is input to the device over just two of the color ports, red and green (r0Cr7 and g0Cg6) and is internally mapped to lut locations 0 to 31 according to figure 26. (note: data on unused pixel inputs is ignored.) microprocessor (mpu) port the adv7150 supports a standard mpu interface. all the functions of the part are controlled via this mpu port. direct access is gained to the address register, mode register and all the control registers as well as the color palette. the following sections describe the setup for reading and writing to all of the devices registers. mpu interface the mpu interface (figure 27) consists of a bidirectional, 10-bit wide databus and interface control signals ce , c0, c1 and r/ w . the 10-bit wide databus is user configurable as illustrated. table ii. databus width table databus ram/dac read/write width resolution mode 10-bit 10-bit 10-bit parallel 10-bit 8-bit 8-bit parallel 8-bit 10-bit 8+2 byte 8-bit 8-bit 8-bit parallel register mapping the adv7150 contains a number of onboard registers includ- ing the mode register (mr17Cmr10), address register (a7C a0) and nine control registers as well as red (r9Cr0), green (g9Cg0) and blue (b9Cb0) color registers. these registers control the entire operation of the part. figure 28 shows the internal register configuration. control lines c1 and c0 determine which register the mpu is accessing. c1 and c0 also determine whether the address reg- ister is pointing to the color registers and look-up table ram or the control registers. if c1, c0 = 1, 0 the mpu has access to whatever control register is pointed to by the address register (a7Ca0). if c1, c0 = 0, 1 the mpu has access to the look-up table ram (color palette) through the associated color regis- ters. the ce input latches data to or from the part. the r/ w control input determines between read or write ac- cesses. the truth tables iii and iv show all modes of access to the various registers and color palette for both the 8-bit wide databus configuration and 10-bit wide databus configuration. it should be noted that after power-up, the devices mpu port is automatically set to 10-bit wide operation (see power-on reset section). color palette accesses data is written to the color palette by first writing to the address register of the color palette location to be modified. the mpu performs three successive write cycles for each of the red, green and blue registers (10-bit or 8-bit). an internal pointer moves from red to green to blue after each write is completed. this pointer is reset to red after a blue write or whenever the address register is written. during the blue write cycle, the three bytes of red, green and blue are concatenated into a single 30-bit/24-bit word and written to the ram location as specified in the ad- dress register (a7Ca0). the address register then automatically increments to point to the next ram location and a similar red, green and blue palette write sequence is performed. the address register resets to 00h following a blue write cycle to color pal- ette ram location ffh.
adv7150 C18C rev. a 30 mpu port d9 ?d0 10 (8+2) c0 c1 addr (a7?0) revision register command registers (cr1?r3) test registers (mr1) data to palettes control registers color registers address register mode register id register blue register pixel mask register ce r/w green register red register figure 27. mpu port and register configuration data is read from the color palette by first writing to the address register of the color palette location to be read. the mpu per- forms three successive read cycles from each of the red, green and blue locations (10-bit or 8-bit) of the ram. an internal pointer moves from red to green to blue after each read is com- pleted. this pointer is reset to red after a blue read or whenever the address register is written. the address register then auto- matically increments to point to the next ram location, and a similar red, green and blue palette read sequence is performed. the address register resets to 00h following a blue read cycle of color palette ram location ffh. register accesses the mpu can write to or read from all of the adv7150s regis- ters. c0 and c1 determine whether the mode register or ad- dress register is being accessed. access to these registers is direct. the control registers are accessed indirectly. the address register must point to the desired control register. figure 28 along with the 8-bit and 10-bit interface truth tables illustrate the structure and protocol for device communication over the mpu port. mode register (mr17?r10) address register (a7?0) address register (a15?0) control registers 00h 01h 02h pixel test register r g b dac test register r g b * this register is read only. a read cycle will return zeros "00". look-up table ram (256 x 30) red register (r9?0) green register (g9?0) blue register (b9?0) points to location corresponding to address reg (a7?0) address reg = address reg + 1 c1 = 1 c0 = 0 c1 = 0 c0 = 1 c1 = 1 c0 = 1 c1 = 0 c0 = 0 sync, blank & i pll test register 03h 04h 05h 06h 07h 08h 09h 0ah 0bh reserved* (read only) reserved* (read only) reserved* (read only) revision register id register (read only) pixel mask register command register 1 command register 2 command register 3 figure 28. internal register configuration and address decoding
adv7150 C19C rev. a table iii. interface truth table (10-bit databus mode) r/ w c1 c0 databus (d9Cd0) operation result 0 1 1 db7Cdb0 write to mode register db7Cdb0 ? mr17Cmr10 0 0 0 db7Cdb0 write to address register db7Cdb0 ? a7Ca0 0 1 0 db7Cdb0 write to control registers db7Cdb0 ? control register ( particular control register determined by address register ) 0 0 1 db9Cdb0 write to red register db9Cdb0 ? r9Cr0 0 0 1 db9Cdb0 write to green register db9Cdb0 ? g9Cg0 0 0 1 db9Cdb0 write to blue register db9Cdb0 ? b9Cb0 write rgb data to ram location pointed to by address register (a7Ca0) address register = address register + 1 1 1 1 db7Cdb0 read mode register mr17Cmr10 ? db7Cdb0 1 0 0 db7Cdb0 read address register a7Ca0 ? db7Cdb0 1 1 0 db7Cdb0 read control registers register data ? db7Cdb0 (particular control register determined by address register) 1 0 1 db9Cdb0 read red ram location r9Cr0 ? db9Cdb0 1 0 1 db9Cdb0 read green ram location g9Cg0 ? db9Cdb0 1 0 1 db9Cdb0 read blue ram location b9Cb0 ? db9Cdb0 (ram location pointed to by address register(a7Ca0)) address register = address register + 1 db = data bit. table iv. interface truth table (8-bit databus mode)* r/ w c1 c0 databus (d7Cd0) operation result 0 1 1 db7Cdb0 write to mode register db7Cdb0 ? mr17Cmr10 0 0 0 db7Cdb0 write to address register db7Cdb0 ? a7Ca0 0 1 0 db7Cdb0 write to control registers db7Cdb0 ? control registers ( particular control register determined by address register ( a7Ca0 )) 0 0 1 db9Cdb2 write to red register db9Cdb2 ? r9Cr2 0 0 1 db1Cdb0 write to red register db1Cdb0 ? r1Cr0 0 0 1 db9Cdb2 write to green register db9Cdb2 ? g9Cg2 0 0 1 db1Cdb0 write to green register db1Cdb0 ? g1Cg0 0 0 1 db9Cdb2 write to blue register db9Cdb2 ? b9Cb2 0 0 1 db1Cdb0 write to blue register db1Cdb0 ? b1Cb0 write rgb data to ram location pointed to by address register (a7-a0) address register = address register + 1 1 1 1 db7Cdb0 read mode register mr17Cmr10 ? db7Cdb0 1 0 0 db7Cdb0 read address register a7Ca0 ? db7Cdb0 1 1 0 db7Cdb0 read control registers register data ? db7Cdb0 (particular control register determined by address register) 1 0 1 db9Cdb2 read red ram location r9Cr2 ? db9Cdb2 1 0 1 db1Cdb0 read red ram location r1Cr0 ? db1Cdb0 1 0 1 db9Cdb2 read green ram location g9Cg2 ? db9Cdb2 1 0 1 db1Cdb0 read green ram location g1Cg0 ? db1Cdb0 1 0 1 db9Cdb2 read blue ram location b9Cb2 ? db9Cdb2 1 0 1 db1Cdb0 read blue ram location b1Cb0 ? db1Cdb0 (ram location pointed to by address register (a7Ca0)) address register = address register + 1 *writing or reading 10-bit data (db9Cdb0) over an 8-bit databus (d7Cd0) requires two write or two read cycles. :db9Cdb2 is mapped to d7Cd0 on the first cycle. :db1Cdb0 is mapped to d1Cd0 on the second cycle. db = data bit.
adv7150 C20C rev. a power-on reset on power-up of the adv7150 executes a power-on reset opera- tion. this initializes the pixel port such that the pixel sequence abcd starts at a. the mode register (mr17Cmr10), com- mand register 2 (cr27Ccr20) and command register 3 (cr37Ccr30) have all bits set to a logic 1. command regis- ter 1 (cr17Ccr10) has all bits set to a logic 0. the output clocking signals are also set during this reset period. prgckout = clock/32 loadout = clock/4 the power-on reset is activated when v aa goes from 0 v to 5 v. this reset is active for 1 m s. the adv7150 should not be accessed during this reset period. the pixel clock should be applied at power-up. register programming the following section describes each register, including address register, mode register and each of the nine control registers in terms of its configuration. address register (a7Ca0) as illustrated in the previous tables, the c0 and c1 control in- puts, in conjunction with this address register specify which control register, or color palette location is accessed by the mpu port. the address register is 8-bits wide and can be read from as well as written to. when writing to or reading from the color palette on a sequential basis, only the start address needs to be written. after a red, green and blue write sequence, the address register is automatically incremented. mode register mr1 (mr19Cmr10) the mode register is a 10-bit wide register. however for pro- gramming purposes, it may be considered as an 8-bit wide regis- ter (mr18 and mr19 are both reserved). it is denoted as mr17Cmr10 for simplification purposes. the diagram shows the various operations under the control of the mode register. this register can be read from as well written to. in read mode, if mr18 and mr19 are read back, they are both returned as zeros. mode register (mr17Cmr10) bit description reset control (mr10) this bit is used to reset the pixel port sampling sequence. this ensures that the pixel sequence abcd starts at a. it is reset by writing a 1 followed by a 0 followed by a 1. this bit must be run through this cycle during the initialization sequence. ram-dac resolution control (mr11) when this is programmed with a 1, the ram is 30 bits deep (10 bits each for red, green and blue) and each of the three dacs is configured for 10-bit resolution. when mr11 is programmed with a 0, the ram is 24-bits deep (8 bits each for red, green and blue) and the dacs are configured for 8-bit resolution. the two lsbs of the 10-bit dacs are pulled down to zero in 8-bit ram-dac mode. mpu databus width (mr12) this bit determines the width of the mpu port. it is configured as either a 10-bit wide (d9Cd0) or 8-bit wide (d7Cd0) bus. 10-bit data can be written to the device when configured in 8-bit wide mode. the 8 msbs are first written on d7Cd0, then the two lsbs are written over d1Cd0. bits d9Cd8 are zeros in 8-bit mode. operational mode control (mr14Cmr13) when mr14 is 0 and mr13 is 1, the part operates in normal mode. calibrate loadin (mr15) this bit automatically calibrates the onboard loadin/ loadout synchronization circuit. a 0 to 1 transition initiates calibration. this bit is set to 0 in normal operation. see pipeline delay and calibration section. this bit must be run through this cycle during the initialization sequence. mr17 mr16 * these bits are read-only reserved bits. a read cycle will return zeros "00." reserved* mr16 ps0 mr17 ps1 palette select match bits control ram-dac resolution control 0 8-bit 1 10-bit mr11 mpu data bus width 0 8-bit (d7?0) 1 10-bit (d9?0) mr12 calibrate loadin mr15 reset control mr10 operational mode control 0 0 reserved 0 1 normal operation 1 0 reserved 1 1 reserved mr14 mr13 mr19 mr18 mr15 mr14 mr13 mr12 mr11 mr10 mode register 1 (mr1) (mr19Cmr10)
adv7150 C21C rev. a palette select match bits control (mr17Cmr16) these bits allow multiple palette devices to work together. when bits ps1 and ps0 match mr17 and mr16 respectively, the device is selected. if these bits do not match, the device is not selected and the analog video outputs drive 0 ma, see palette priority select inputs section. control registers the adv7150 has 9 control registers. to access each register, two write operations must be performed. the first write to the address register specifies which of the 9 registers is to be ac- cessed. the second access determines the value written to that particular control register. pixel test register (address reg (a7Ca0) = 00h) this register is used when the device is in test/diagnostic mode. it is a 24-bit (8 bits each for red, green and blue) wide read-only register which allows the mpu to read data on the pixel port, see test diagnostic section. dac test register (address reg (a7Ca0) = 01h) this register is used when the device is in test/diagnostic mode. it is a 30-bit (10 bits each for red, green and blue) wide read-only register which allows mpu access to the dac port, see test diagnostic section. sync , blank and i pll test register (address reg (a7Ca0) = 02h) this register is used when the device is in test/diagnostic mode. it is a 3-bit wide (3 lsbs) read/write register which allows mpu access to these particular pixel control bits, see test diagnos- tic section. id register (address reg (a7Ca0) = 03h) this is an 8-bit wide identification read-only register. for the adv7150 it will always return the hexadecimal value 8eh. pixel mask register (address reg (a7Ca0) = 04h) the contents of the pixel mask register are individually bit-wise logically and-ed with the red, green and blue pixel input stream of data. it is an 8-bit read/write register with d0 corre- sponding to r0, g0 and b0. for normal operation, this register is set with ffh. command register 1 (cr1) (address reg (a7Ca0) = 05h) this register contains a number of control bits as shown in the diagram. cr1 is a 10-bit wide register. however for program- ming purposes, it may be considered as an 8-bit wide register (cr18 to cr19 are reserved). the diagram below shows the various operations under the con- trol of cr1. this register can be read from as well as written to. in write mode, 0 should be written to cr11 and cr13 to cr17. in read mode, cr11 and cr13 to cr19 are returned as zeros. command register 1-bit description calibration control (cr10) this bit automatically calibrates the onboard loadin/ loadout synchronization circuit. mr15 of mode register mr1 must be set to 0. syncout control (cr12) this bit specified whether the video syncout signal is to be enabled. on power up a 0 is written to the bit and syncout is set three-state. *these bits are read?nly reserved bits. a read cycle will return zeros "00." cr12 0 disable 1 enable syncout syncout control cr17 cr16 cr15 cr14 cr12 cr11 cr10 cr13 reserved* cr11 (0) this bit should be set to zero calibration control cr10 0 1 disable calibrates on every vertical sync (mr15=0) cr17-cr13 (00000) these bits should be set to zero cr18 cr19 command register 1 (cr1) (cr19Ccr10)
adv7150 C22C rev. a command register 2 (cr2) (address reg (a7Ca0) = 06h) this register contains a number of control bits as shown in the diagram. cr2 is a 10-bit wide register. however, for program- ming purposes, it may be considered as an 8-bit wide register (cr28 and cr29 are both reserved). the diagram shows the various operations under the control of cr2. this register can be read from as well written to. in read mode, cr28 and cr29 are both returned as zeros. command register 2-bit description r7 trigger polarity control (cr20) this bit is used when the device is in test/diagnostic mode. it determines whether the pixel data is latched into the test regis- ters in the rising or falling edge of r7. (see test diagnostics section.) i pll trigger control (cr21) this bit specifies whether the i pll output is triggered from blank or sync . sync recognition control (cr22) this bit specifies whether the video sync input is to be encoded onto the iog analog output or ignored. pedestal enable control (cr23) this bit specifies whether a 0 ire or a 7.5 ire blanking pedes- tal is to be generated on the video outputs. true-color/pseudo-color mode control (cr27Ccr24) these 4 bits specify the various color modes. these include a 24-bit true-color mode, two 15-bit true-color modes and three 8-bit pseudo color modes. cr20 reserved* cr26 cr25 cr24 cr27 0 1 cr21 i pll trigger control sync blank r7 trigger polarity control 0 1 cr20 cr29 cr28 cr22 0 ignore 1 decode sync recognition control *these bits are read- only reserved bits. a read cycle will return zeros "00." cr21 cr23 cr22 true color/pseudo-color mode control mode 0 1 1 1 10 00 1 000 1101 cr27 cr26 cr24 cr25 1100 0 0 00 8-bit pseudo color on r7?0 8-bit pseudo color on g7?0 8-bit pseudo color on b7?0 15-bit true color on r7?3, g7?3, b7?3 15-bit true color on r7?0, g6?0 24-bit true color r7?0, g7?0, b7?0 pedestal enable control cr23 0 0 ire 1 7.5 ire command register 2 (cr2) (cr29Ccr20)
adv7150 C23C rev. a command register 3 (cr3) (address reg (a7Ca0) = 07h) this register contains a number of control bits as shown in the diagram. cr3 is a 10-bit wide register. however for program- ming purposes, it may be considered as an 8-bit wide register (cr38 and cr39 are both reserved). the diagram shows the various operations under the control of cr3. this register can be read from as well written to. in read mode, cr38 and cr39 are both returned as zeros. command register 3-bit description prgckout frequency control (cr31Ccr30) these bits specify the output frequency of the prgckout output. prgckout is a divided down version of the pixel clock. blank pipeline delay control (cr35Ccr32) these bits specify the additional pipeline delay that can be added to the blank function, relative to the overall device pipeline delay (t pd ). as the blank control normally enters the video dac from a shorter pipeline than the video pixel data, this control is useful in deskewing the pipeline differential. pixel multiplex control (cr37Ccr36) these bits specify the devices multiplex mode. it, therefore, also determines the frequency of the loadout signal. loadout is a divided down version of the pixel clock. revision register (address reg (a7Ca0) = 0bh) this register is a read only register containing the revision of silicon. cr39 cr38 cr37 cr36 cr35 cr34 cr32 cr31 cr30 cr33 *these bits are read- only reserved bits. a read cycle will return zeros "00." prgckout frequency control cr31 cr30 0 0 1 1 0 1 0 1 clock ? 4 clock ? 8 clock ? 16 clock ? 32 reserved* pixel multiplex control cr37 cr36 0 0 1 1 0 1 0 1 1:1 muxing: loadout = clock ? 1 2:1 muxing loadout = clock ? 2 reserved 4:1 muxing :loadout = clock ? 4 extra blank pipeline delay control (adds to pixel pipeline delay; t pd ) cr35 cr34 cr33 cr32 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 t pd t pd + 1 x loadout t pd + 2 x loadout t pd + 15 x loadout command register 3 (cr3) (cr39Ccr30)
adv7150 C24C rev. a digital-to-analog converters (dacs) and video outputs the adv7150 contains three high speed video dacs. the dac outputs are represented as the three primary analog color signals ior (red video), iog (green video) and iob (blue video). other analog signals on the part include i pll and v ref as well as complementary video outputs ior , iog , iob . these comple- mentary outputs can be used to drive differentially terminated video loads, they will have equal but opposite output levels to ior, iog and iob when loaded with a resistive load similar to ior, iog and iob. dacs and analog outputs the part contains three matched 10-bit digital-to-analog con- verters. the dacs are designed using an advanced, high speed, segmented architecture. the bit currents corresponding to each digital input are routed to either ior, iog, iob (bit = l) or i or , iog , iob (bit = 0). (normally ior , iog , iob = gnd.) the analog video outputs are high impedance current sources. each of the these three rgb current outputs are specified to directly drive a 37.5 w load (doubly terminated 75 w ). dacs ior, iog, iob z o = 75 w z s = 75 w (source termination) z l = 75 w (monitor) (cable) figure 29. dac output termination (doubly terminated 75 w load) reference input and r set an external 1.23 v voltage reference is required to drive the analog outputs of the adv7150. the reference voltage is con- nected to the v ref input. a resistor r set is connected between the r set input of the part and ground. for specified performance, r set has a value of 280 w . this corresponds to the generation of rs-343a video levels (with sync on iog and pedestal = 7.5 ire) into a dou- bly terminated 75 w load. figure 30 illustrates the resulting video waveform, and the video output truth table shows the corresponding control input stimuli. white level ior, iob iog ma ma v v 26.67 1.000 0.714 19.05 00 00 7.62 0.286 blank level sync level gray scale 92.5 ire 7.5 ire 40 ire black level 1.44 0.054 9.05 0.340 figure 30. composite video waveform ( sync decoded on iog; pedestal = 7.5 ire; r set = 280 w ) variations on rs-343a various other video output configurations can be implemented by the adv7150, including rs-170. values of r set for particu- lar output video formats/levels are calculated by using the equa- tions for r set given in the pin configuration section. the table shows calculated values of r set for some of the most com- mon variants on the rs-343a standard. the associated wave- forms are shown in the diagrams. table v. video output truth table iog ior, iob dac description (ma) (ma) sync blank input data white level 26.67 19.05 1 1 3ffh video video + 9.05 video + 1.44 1 1 data video to blank video + 1.44 video + 1.44 0 1 data black level 9.05 1.44 1 1 000h black to blank 1.44 1.44 0 1 000h blank level 7.62 0 1 0 xxxh sync level 0 0 0 0 xxxh decoded on iog; pedestal = 0 ire; r set = 265 w .
adv7150 C25C rev. a white level 100 ire 43 ire ior, iob iog ma ma v v 26.67 1.000 0.698 18.62 00 00 8.05 0.302 black/ blank level sync level gray scale figure 31. composite video waveform sync white level black level 92.5 ire 7.5 ire ior, iob, iog ma v 19.05 0.714 00 1.44 0.054 blank level gray scale figure 32. composite video waveform (pedestal = 7.5 ire; r set = 280 w ) white level 100 ire ior, iob, iog ma v 19.05 0.714 00 black/ blank level gray scale figure 33. composite video waveform (pedestal = 0 ire; r set = 259 w ) r set ( v ) video signal 265 sync decoded on iog; pedestal = 0 ire 280 no sync decoded; pedestal = 7.5 ire 259 no sync decoded; pedestal = 0 ire i pll synchronization output control this output synchronization signal is used in applications where it is necessary to synchronize multiple palette devices (adv7150 + adv7151) to subpixel resolution. each devices i pll output signal is in phase with its analog rgb output signal. if multiple devices have differing output delays, the time difference can be derived from the i pll signals. this time difference is then used to phase shift the clock inputs on one or other of the devices inputs. the i pll signal is internally triggered by either the falling edge of sync or blank as determined by cr21 of command register 2.
adv7150 C26C rev. a appendix 1 board design and layout considerations v aa v ref r set ior iog iob i pll gnd comp ior iog iob r set 280 w 1k w (1% metal) ad589 (1.2v ref) 0.1 m f +5v (v aa ) 75 w 75 w 75 w 75 w 75 w 75 w complimentary outputs co-axial cable (75 w ) bnc connectors monitor (crt) +5v (v aa ) 0.1 m f analog power plane 33 m f 0.1 m f 0.01 m f 0.1 m f 0.01 m f 0.1 m f 0.01 m f 0.1 m f 0.01 m f +5v (v aa ) 0.1 m f +5v (v cc ) l1 (ferrite bead) notes: 1. all resistors are 1% metal film 2. 0.1 m f and 0.01 m f capacitors are ceramic 3. additional digitalcircuitry omitted for clarity adv7150 power supply decoupling (0.1 m f and 0.01 m f capacitor for each v aa group) recommended analog circuit layout power plane (v cc ) at a single point through a ferrite bead. this bead should be located within three inches of the adv7150. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7150 power pins and voltage reference circuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. supply decoupling for optimum performance, bypass capacitors should be i nstalled using the shortest leads possible, consistent with reliable opera- tion, to reduce the lead inductance. best performance is obtained with 0.1 m f ceramic capacitor decoupling. each group of v aa pins on the adv7150 must have at least one 0.1 m f decoupling capacitor to gnd. these capacitors should be placed as close as possible to the device. it is important to note that while the adv7150 contains cir- cuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reducing power sup- ply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane. the adv7150 is a highly integrated circuit containing both precision analog and high speed digital circuitry. it has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. it is impera- tive that these same design and layout techniques be applied to the system level design such that high speed, accurate perfor- mance is ac hieved. the recommended analog circuit layout shows the analog interface between the device and monitor. the layout should be optimized for lowest noise on the adv7150 power and ground lines by shielding the digital inputs and pro- viding good decoupling. the lead length between groups of v aa and gnd pins should by minimized so as to mi nimize inductive ringing. ground planes the ground plane should encompass all adv7150 ground pins, voltage reference circuitry, power supply bypass circuitry for the adv7150, the analog output traces, and all the digital signal traces leading up to the adv7150. the ground plane is the graphics boards common ground plane. power planes the adv7150 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (v aa ). this power plane should be connected to the regular pcb
adv7150 C27C rev. a digital signal interconnect the digital inputs to the adv7150 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane. due to the high clock rates involved, long clock lines to the adv7150 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ), and not the analog power plane. analog signal interconnect the adv7150 should be located as close as possible to the out- put connectors to minimize noise pick-up and reflections due to impedance mismatch. the video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. digital inputs, especially pixel data inputs and clocking signals (clock, loadout, loadin, etc.) should never overlay any of the analog signal circuitry and should be kept as far away as possible. for best performance, the analog outputs (ior, iog, iob) should each have a 75 w load resistor connected to gnd. these resistors should be placed as close as possible to the adv7150 so as to minimize reflections. normally, the differen- tial analog outputs ( ior , iog , io b) are connected directly to gnd. in some applications, improvements in performance are achieved by terminating these differential outputs with a resis- tive load similar in value to the video load. for a doubly termi- nated 75 w load, this means that ior , iog , iob are each terminated with 37.5 w resistors. appendix 2 typical frame buffer interface clock adv7150 clock loadout prgckout loadin sckout sckin blank latch enable sync ecl to ttl divide by n ( ? n) vram (bank a) vram (bank b) frame buffer/ video memory multiplexer 24 to palette/ram & dac 24 24 24 24 blank sync clock graphics processor/ controller vram (bank c) 24 24 vram (bank d) 24 24 33mhz 33mhz 33mhz 33mhz divide by m ( ? m) clock generator
adv7150 C28C rev. a 10-bit dacs 10-bit ram-dac resolution allows for nonlinear video correc- tion, in particular gamma correction. the adv7150 allows for an increase in color resolution from 24-bit to 30-bit effective color without the necessity of a 30-bit deep frame buffer. in true-color mode, for example, the part effectively operates as a 24-bit to 30-bit color look-up table. up to now we have assumed that there exists a linear relation- ship between the actual rgb values input to a monitor and the intensity produced on the screen. this, however, is not the case. half scale digital input (1000 0000) might correspond to only 20% output intensity on the crt (cathode ray tube). the intensity (i crt ) produced on a crt by an input value i in is given by: i crt = ( i in ) c where c ranges from 2.0 to 2.8. if the individual values of c for red, green and blue are known, then so called gamma correction can be applied to each of the three video input signals (i in ); therefore: i in(corrected) = k ( i in ) 1/ c (k = 1, normally) traditionally, there has been a tradeoff between implementing a nonlinear graphics function, such as gamma correction, and color dynamic range. the adv7150 overcomes this by increas- ing the individual color resolution of each of the red, green and blue primary colors from 8 bits per color channel to 10 bits per channel (24 bits to 30 bits). the table highlights the loss of resolution when 8-bit data is gamma-corrected to a value of 2.7 and quantized in a tradi- tional 8-bit system. note that there is no change in the 8-bit quantized data for linear changes in the input data over much of the transfer function. on the other hand, when quantized to 10 bits via the 10-bit rams and 10-bit dacs of the adv7150, all changes on the input 8-bit data are reflected in corresponding changes in the 10-bit data. the graph shows a typical gamma curve corresponding to a gamma value of 2.7. this is programmed to the red, green and blue rams of the color lookup table instead of the more tradi- tional linear function. different curves corresponding to any particular gamma value can be independently programmed to each of the red, green and blue rams. other applications of the 10-bit ram-dac include closed-loop monitor color calibration. gamma correction 8 bits vs. 10 bits gamma corrected quantized to quantized to 8-bit data (2.7) 8 bits 10 bits 240 0.977797 250 1001 241 0.979304 250 1002 242 0.980807 251 1004 243 0.982306 251 1005 244 0.983801 251 1007 245 0.985292 252 1008 246 0.986780 252 1010 247 0.988264 252 1011 248 0.989744 253 1013 249 0.991220 253 1015 250 0.992693 254 1016 251 0.994161 254 1018 252 0.995626 254 1019 253 0.997088 255 1021 254 0.998546 255 1022 255 1.000000 255 1023 1.00 0.00 256 0.30 0.10 32 0.20 0 0.60 0.40 0.50 0.70 0.80 0.90 224 192 160 128 96 64 input code ?decimal dac output ?normalized to 1 gamma correction curve linear response preceived by the eye crt response gamma correction curve (gamma value = 2.7) appendix 3 10-bit dacs and gamma correction
adv7150 C29C rev. a appendix 4 multiple palette applications palette priority select inputs the palette priority selection inputs allow up to four separate palette devices to be used in a single system to drive a single monitor with subpixel resolution. the ior, iog and iob ana- log video output signals of each device are connected together, as shown. signal inputs (ps0, ps1) determine on a pixel by pixel basis which palette device drives the monitor. this allows for implementation of multiple windows applications with each device acting as an in dependent palette. during initialization, each device is assigned two match bits, mr16 (ps0) and mr17 (ps1) in mode register mr1. ps0 and ps1 inputs will select one of the preprogrammed devices at any instant when ps0, ps1 matches mr16, mr17, respectively. ps0 and ps1 are multi- plexed similar to the pixel data, thus allowing for subpixel resolu- tion. the diagrams show an example of one adv7150 operating in conjunction with three adv7151s (pseudo-color ram-dacs). each displayed window on the monitor is driven by one of the four devices, as determined on a pixel basis by ps0, ps1. each devices analog output signals are connected together as shown. note: o nly one palette device is selected at any particular instant. the analog output levels of the unselected devices will be 0 ma. other applications for the palette priority function using a mini- mum of two devices (one adv7150 and one adv7151) include: cursor overlay on 24-bit graphics active live video overlay (from frame grabber) text/character generation and overlay dacs ior, iog, iob z o = 75 w z s = 75 w (source termination) z l = 75 w (monitor) (cable) dacs ior, iog, iob (device: 2) (device: 1) multiple devices termination for a single monitor adv7150 adv7151 (1) 256 x 30 ram 256 x 30 palette palette select bits analog o/p rgb analog video video to monitor ps0, ps1 256 x 30 palette rgb analog video rgb analog video adv7151 (2) adv7151 (3) r0?7 g0?7 b0?7 window 1 (pseudo-color) ps0=0: ps1=1 window 3 (pseudo-color) ps0=1: ps1=1 monitor window 2 (pseudo-color) ps0=1: ps1=0 true-color background mr16 mr17 0 0 palette select bits mr16 mr17 0 1 palette select bits mr16 mr17 1 0 palette select bits mr16 mr17 1 1 256 x 30 palette p0?7 multiple devices driving a multiwindow application
adv7150 C30C rev. a adv7150 initialization after power has been supplied, the adv7150 must be initial- ized. the mode register and control registers must be set. the values written to the various registers will be determined by the desired operating mode of the part, i.e., true color/pseudo color, 2:1 muxing/2:1 muxing, etc. the following section gives examples of initialization of the adv7150 operating in various modes. example 1 color mode 24-bit true color multiplexing 2:1 databus 8-bit ram-dac resolution 8-bit sync enabled on iog pedestal 7.5 ire register initialization c1 c0 r/ w comment write 09h to mode register (mr1) 1 1 0 resets to normal operation, 8-bit bus/ram-dac write 08h to mode register (mr1) 1 1 0 *(initializes pipelining write 09h to mode register (mr1) 1 1 0 *( write 29h to mode register (mr1) 1 1 0 *(calibrates loadout/loadin timing write 09h to mode register (mr1) 1 1 0 *( write 04h to address register (a7Ca0) 0 0 0 address reg points to pixel mask register write ffh to pixel mask register 1 0 0 sets the pixel mask to all 1s write 05h to address register (a7Ca0) 0 0 0 address reg points to command register 1 (cr1) write 00h to command reg 1 (cr1) 1 0 0 write 06h to address register (a7Ca0) 0 0 0 address reg points to command register 2 (cr2) write ech to command reg 2 (cr2) 1 0 0 sets 24-bit color, 7.5 ire, sync on green (iog) write 07h to address register (a7Ca0) 0 0 0 address reg points to command register 3 (cr3) write c0h to command reg 3 (cr3) 1 0 0 sets 2:1 multiplexing, prgckout = clock/4 color palette ram initialization c1 c0 r/ w comment write 00h to address register (a7Ca0) 0 0 0 points to color palette ram write 00h (red data) to ram location (00h) 0 1 0 (initializes palette ram write 00h (green data) to ram location (00h) 0 1 0 ( to a linear ramp** write 00h (blue data) to ram location (00h) 0 1 0 ( write 01h (red data) to ram location (01h) 0 1 0 ( write 01h (green data) to ram location (01h) 0 1 0 ( write 01h (blue data) to ram location (01h) 0 1 0 ( ? ??? ? ???( ? ??? ? ???( write ffh (red data) to ram location (ffh) 0 1 0 ( write ffh (green data) to ram location (ffh) 0 1 0 ( write ffh (blue data) to ram location (ffh) 0 1 0 (ram initialization complete * *these four command lines reset the adv7150. the pipelines for each of the red, creen and blue pixel inputs are synchronously reset to the multiplexers a input. mode register bit mr10 is written by a 1 followed by 0 followed by 1. loadin/loadout timing is internally synchronized by writing a 0 followed by a 1 followed by a 0 to mode register mr15. **this sequence of instructions would, of course, normally be coded using some form of loop instruction. appendix 5 initialization and programming
adv7150 C31C rev. a example 2 color mode 24-bit gamma corrected true color (30 bits) multiplexing 2:1 databus 10 bit ram-dac resolution 10 bit sync ignored pedestal 0 ire calibration every vertical sync register initialization c1 c0 r/ w comment write 0fh to mode register (mr1) 1 1 0 resets to normal operation, 10-bit bus/ram-dac write 0eh to mode register (mr1) 1 1 0 *(initializes pipelining write 0fh to mode register (mr1) 1 1 0 *( write 2fh to mode register (mr1) 1 1 0 *(calibrates loadout/loadin timing write 0fh to mode register (mr1) 1 1 0 *( write 04h to address register (a7Ca0) 0 0 0 address reg points to pixel mask register write ffh to pixel mask register 1 0 0 sets the pixel mask to all 1s write 05h to address register (a7Ca0) 0 0 0 address reg points to command register 1 (cr1) write 01h to command reg 1 (cr1) 0 0 0 calibrates every vertical sync write 06h to address register (a7Ca0) 0 0 0 address reg points to command register 2 (cr2) write e0h to command reg 2 (cr2) 1 0 0 sets 24-bit color, 0 ire, no sync write 07h to address register (a7Ca0) 0 0 0 address reg points to command register 3 (cr3) write 41h to command reg 3 (cr3) 1 0 0 sets 2:1 multiplexing, prgckout = clock /8 color palette ram initialization c1 c0 r/ w comment write 00h to address register (a7Ca0) 0 0 0 points to color palette ram write 000h (red data) to ram location (00h) 0 1 0 (initializes palette ram write 000h (green data) to ram location (00h) 0 1 0 ( to a gamma ramp** write 000h (blue data) to ram location (00h) 0 1 0 ( write xxxh (red data) to ram location (01h) 0 1 0 ( write xxxh (green data) to ram location (01h) 0 1 0 ( write xxxh (blue data) to ram location (01h) 0 1 0 ( ? ??? ? ???( ? ??? ? ???( write 3ffh (red data) to ram location (ffh) 0 1 0 ( write 3ffh (green data) to ram location (ffh) 0 1 0 ( write 3ffh (blue data) to ram location (ffh) 0 1 0 (ram initialization complete * *these four command lines reset the adv7150 the pipelines for each of the red, green and blue pixel inputs are synchronously reset to the multiplexers a in- put. mode register bit mr10 is written by a 1 followed by 0 followed by 1. loadin/loadout timing is internally synchronized by writing a 0 followed by a 1 followed by a 0 to mode register mr15. **data for a gamma curve characteristic is obtainable in appendix 3. register diagnostic testing the previous examples show the register initialization sequence for the adv7150. these show control data going to the regis- ters and palette ram. as well as this writing function, it may also be necessary, due to system diagnostic requirements, to confirm that correct data has been transferred to each register and palette ram location. there are two ways to incorporate register value/ram value checking: 1 . read after each write: after data is written to a particular register, it can be read back immediately. the following table shows an example with command registers cr2 and cr3. c1 c0 r/ w d0Cd7 comment 0 0 0 06h select command register 2 (cr2) 1 0 0 e0h sets 24-bit true-color 1 0 1 e0h command reg 2 value read-back 0 0 0 07h select command register 3 (cr3) 1 0 0 40h set 2:1 mux mode 1 0 1 40h command reg 3 value read-back 2. read after all writes completed: all registers and the color palette ram are written to and set. once this is complete, all registers are again accessed but this time in read-only mode. the table below shows this method for command registers cr2 and cr3. c1 c0 r/ w d0Cd7 comment 0 0 0 06h select command register 2 (cr2) 1 0 0 e0h sets 24-bit true-color 0 0 0 07h select command register 3 (cr3) 1 0 0 40h set 2:1 mux mode 0 0 0 06h select cr2 1 0 1 e0h cr2 value read-back 0 0 0 07h select cr3 1 0 1 40h cr3 value read-back 1 0 1 40h cr3 value read-back it is clear that this latter case requires more command lines than the previous read after each write case.
adv7150 C32C rev. a the graphics pipeline and after a number of clocks get latched into the dac test register. this data can then be read from the pixel test register and the dac test registers over the mpu port. this data will remain in the pixel test registers and the dac test registers until the next rising edge of r7 causes new data to be latched in. in the above example, the next rising edge of r7 occurs on the pixel n input. therefore the data in the pixel test registers and dac test registers must be read over the mpu before the pixel n data is applied, otherwise they will be overwritten by the pixel n data and the pixel 2 data will be lost. pixel test register the read-only pixel test register is 24 bits wide, 8 bits each for red green and blue. it is situated directly after the pixel mask register. after data is latched into this register by a transition on r7, it is read in three cycles over the mpu port as described in the microprocessor (mpu) port section. dac test register the dac test register is latched with data some clocks after the pixel test register. the dac test register is a 30-bit wide read-only register, corresponding to 10 bits each for red, green and blue data. it is located the color palette ram. if the ram-dac is in 8-bit after resolution mode, the upper two bits of the red, green and blue data will be zero. after data is latched into the dac test register by a transition on r7, it is read in three or six cycles over the mpu port as described in the microprocessor (mpu) port section. sync , blank and i pll test register this is an 8-bit wide register but with only three effective bits. the three lower bits correspond to sync , blank and i pll respectively. the upper bits should be masked in software. this register is at the same position in the graphics pipeline as the dac test register. when pixel data is latched into the dac test register, the corresponding status of sync , blank and i pll is latched into this register. it is read over the mpu port as described in the microprocessor (mpu) port section. (note: if blank is low, the corresponding pixel data to the dac test register will be all 0s.) the adv7150 contains onboard circuitry which enables both device and system level test diagnostics. the test circuitry can be used to test the frame buffer memory as well as the function- ality of the adv7150. a number of test registers are integrated into the part which effectively allow for monitoring of the graph- ics pipeline. pixel data is read from the graphics pipeline inde- pendent of the pixel clock. the pixel data itself contains the triggering information that latches data into the test registers. this allows for system diagnostics in a continuously clocked graphics system. the test register data is then read by the micro- processor over the mpu. access to the test registers is as described in the microproces- sor (mpu) port section. this section also gives the address decode locations for the various test registers. test trigger (r7) the test trigger is decoded from the pixel data stream. bit r7 of the red channel is assigned the task of latching pixel data into the test registers. a 0 to 1 or a 1 to 0 (as determined by bit cr20 of command register 2) transition on r7, fills the test register with the corresponding pixel data. this effectively means that a sequence of data travels along the graphics pipe- line, with the test registers taking a sample only when there is a transition on bit r7. the following example shows a sequence with the adv7150 preset to sample the graphics pipeline on a low to high transition of r7. red green blue pixel 0: 00000000 00000000 00000000 pixel 1: 0........ ........ ........ pixel 2: 1........ ........ ........ pixel 3: 0........ ........ ........ .... ... .... ... pixel n- l: 0........ ........ ........ pixel n: 1........ ........ ........ pixel n: 0........ ........ ........ in the above sequence of pixels, there is a rising edge on r7 on pixel 2. the red, green and blue data for pixel 2, therefore, gets latched into the pixel test register. pixel 2 continues down appendix 6 test diagnostics mpu port ce r/w c0 c1 d0?9 pixel test register dac test registers color registers color palette ram trigger decode trigger decode graphics pipeline graphics pipeline input mux pixel data sync blank dacs sync blank i pll register test test/diagnostic block diagram
adv7150 C33C rev. a appendix 7 thermal and environmental considerations the adv7150 is a very highly integrated monolithic silicon device. this high level of integration, in such a small package, inevitably leads to consideration of thermal and environmental conditions in which the adv7150 must operate. reliability of the device is significantly enhanced by keeping it as cool as pos- sible. in order to avoid destructive damage to the device, the absolute maximum junction temperature of 150 c must never be exceeded. certain applications, depending on pixel data rates, may require forced air cooling, or external heatsinks. the following data is intended as a guide in evaluating the operating conditions of a particular application so that optimum device and system performance is achieved. i t should be noted that information on package characteristics pub- lished herein may not be the most up to date at the time of reading this. advances in package compounds and manufacture will inevita- bly lead to improvements in the thermal data. please co ntact your local sales office for the most up-to-date information. power dissipation the diagram shows graphs of power dissipation in watts vs. pixel clock frequency for the adv7150. power dissipation ?w atts 1.50 0.50 1.25 0.75 1.00 pixel clock frequency ?mhz 60 220 80 180 200 160 140 120 100 v aa = 5v v ref = 1.2v t a = +25 c note: the "worst case on-screen pattern" corresponds to full-scale transition on each pixel value for every clock edge (00h, ffh, 00h, ... ). the "typical on-screen pattern" corresponds to linear changes in the pixel input (i. e., a black to white ramp). in general, color images tend to approximate this characteristic. typical power dissipation vs. pixel rate package characteristics the table of thermal characteristics shows typical information for the adv7150 (160-lead plastic power qfp) using various values of airflow. junction to case ( q jc ) thermal resistance for this particular part is: q jc ( 160-lead plastic power qfp) = 1.0 c/w (note: q jc is independent of airflow.) table a. thermal characteristics vs. airflow air velocity 0 50 100 200 (linear feet/min) (still air) q ja ( c/w) no heatsink 25.5 23 21 19 eg&g d10100-28 heatsink 23 20 18 16 thermalloy 2290 heatsink 19 17 15 12 thermal model the junction temperature of the device in a specific application is given by: t j = t a + p d ( q jc + q ca ) (1) or t j = t a + p d ( q ja ) (2) where: t j = junction temperature of silicon ( c) t a = ambient temperature ( c) p d = power dissipation (w) q jc = junction to case thermal resistance ( c/w) q ca = case to ambient thermal resistance ( c/w) q ja = junction to ambient thermal resistance ( c/w) package enhancements the standard qfp package has been enhanced to a powerquad2 package. this supports an improved thermal performance com- pared to standard qfp. in this case, the die is attached to heatslug so that the power that is dissipated can be conducted to the external surface of the package. this provides a highly effi- cient path for the transfer of heat to the package surface. the package configuration also provides an efficient thermal path from the adv7150 to the printed circuit board via the leads. heatsinks the maximum silicon junction temperature should be limited to 100 c. temperatures greater than this will reduce long term device reliability. to ensure that the silicon junction tempera- ture stays within prescribed limits, the addition of an external heatsink may be necessary. heatsinks, will reduce q ja as shown in the thermal characteristics vs. airflow table.
adv7150 C34C rev. a appendix 8 outline dimensions dimensions shown in inches and (mm). s-160 160-lead plastic power quad flatpack top view (pins down) pin 1 121 160 1 120 41 40 80 81 0.014 (0.35) 0.011 (0.27) 1.239 (31.45) 1.219 (30.95) 1.107 (28.10) 1.100 (27.90) sq sq 0.026 (0.65) min seating plane 0.160 (4.07) max 0.037 (0.95) 0.026 (0.65) 0.004 (0.10) max 0.145 (3.67) 0.125 (3.17) 0.070 (1.77) 0.062 (1.57) 0.070 (1.77) 0.062 (1.57) 10 6 4 4 4 max
C35C
c1695C10C8/94 printed in u.s.a. C36C rev. a

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